sureCore taps Sarcina for cryo packaging

After Sheffield cryo chip specialist sureCore’s launch of a range of cryogenic IP in 180 nm and 22nm test chips, the company has teamed with packaging specialist Sarcina who designed a custom package specifically for use at cryogenic temperatures.

“This represents another critical step in our programme to make Cryo-CMOS available for the Quantum Computing (QC) ecosystem,” says sureCore CEO Paul Wells, “our CryoMemrange of memory IP is silicon proven in addition to validating our library re characterisation service. We are also offering a range of cryogenic design capabilities to help QC companies design the control/interface chips which need to be migrated into the cryostat alongside the qubits.”

.sureCore has created embedded SRAM capable of operating from 77K (-196°C) down to the near absolute zero temperatures needed by Quantum Computers (QCs).

Standard  cell and IO cell libraries have been re-characterised for operation at cryogenic temperatures thereby enabling an industry standard RTL to GDSII physical design flow to be readily adopted.

A key barrier to QC scaling is being able to collocate ever increasingly complex control electronics close to the qubits that must be housed at cryogenic temperatures in a cryostat. In doing so, it is essential that the control chip power consumption is kept as low as possible to ensure that excess heat is kept to a minimum so it does not cause additional thermal load on the cryostat.

.Current QC designs have the control electronics located outside the cryostat as modern semiconductor technology is only qualified to work down to -40°C. As the temperature is reduced close to absolute zero the operating characteristics of the transistors change markedly. Measuring, understanding and modelling this behavioural change over the past months showcases the potential to build interface chips that can control and monitor qubits at cryogenic temperatures.

At the moment, expensive bulky cabling connects room temperature control electronics to the qubits housed in the cryostat. Enabling QC developers to be able to exploit the fabless design paradigm and create their own custom cryogenic control SoCs, which can be housed with the qubits inside the cryostat will  enable QC scaling.

Immediate benefits include cost, size and, most importantly, latency reduction. The next step will be characterising the demonstrator chip at cryo temperatures to further refine and validate the models to help improve the performance.”