Rapidus and Synopsys deliver shortened design cycle
Rapidus, the Japanese startup pursuing 2nm technology, and Synopsys say they have developed a method to shorten the IC design cycle.
11 Dec 08:04 · Electronics Weekly.com
IP meets low latency HPA and AI design demands
Based on Synopsys’ Ethernet and PCIe IP, the Ultra Ethernet IP help developers of AI/HPC infrastructure chips and systems.
11 Dec 16:35 · Electronics Weekly.com
last updated on 12 Dec 07:56